The present invention relates to semiconductor technology, and more specifically, to circuits and processes for maximizing 3D yield from a wafer to wafer stack.
One of the primary goals of semiconductor providers is to provide quality semiconductor devices at minimum cost. Semiconductor devices are major components in most, if not all, end user products. Because of this pervasive use, the cost of semiconductor devices directly affects the overall cost of user products. A relatively low cost semiconductor device could reduce the price of end user products; whereas a relatively high cost semiconductor device could increase the price of end user products. As is well known, the low cost providers of quality products are most likely to succeed in the market-place.
As a result of this interrelation between cost of components and the cost of end products, the providers of semiconductor products or components are constantly looking for ways to lower component cost. It has been determined that maximizing the yield of semiconductor products, preferably during design and fabrication, has a direct effect on the cost of the product. As yield increases, the price of the semiconductor product decreases and vice versa. Wafer stacking is one of the solutions in 3D integration technology that has the potential to lower cost, lower power, and improve performance. However, it is necessary to observe certain rules during the stacking, bonding, and dicing of the wafers as the rules could have a large impact on yield and cost, thereby decreasing the value of 3D stacking. One of the important rules of stacking is that the resulting stack must include only functional or good die. If a non functional or bad die is included in the stack, the entire stack could be non functional and may have to be electronically repaired, reworked or, in the worst case, discarded as stack yield loss. Either way, stacked die yield must be maximized to maintain or reduce cost. Therefore, all aspects of wafer to wafer stacking will have to be addressed in order to reap full benefits from the 3D stacking process. The other aspects and solutions to maximize yield are addressed according to an embodiment of our invention set forth below.